1. Field of the Invention
The present invention relates to a semiconductor device having circuits composed of thin-film transistors. More particularly, the present invention relates to an electro-optical device represented by a liquid-crystal display unit and also to a structure of electronic machines and equipment equipped with such electro-optical devices. The term xe2x80x9csemiconductor devicexe2x80x9d as used in this specification generally denotes any device which functions by utilizing the semiconductor characteristics and hence it embraces said electro-optical devices and electronic machines and equipment equipped with said electro-optical devices.
2. Description of the Related Arts
Considerable efforts have been directed to the application of thin-film transistors (TFT for short hereinafter) to liquid crystal display units of active matrix type because of their ability to be formed on a transparent glass substrate. TFTs based on polysilicon film have such high mobility that they are expected to give a precision image if their functional circuits are integrated on a single substrate.
A liquid crystal display unit of active matrix type needs as many TFTs as million for pixels alone if it is to produce an image of high resolution. When it is provided with functional circuits, it needs more TFTs. For its stable operation, it requires individual TFTs to work with good stability and reliability.
In a liquid crystal display unit of active matrix type, each pixel is constructed of n-channel type TFT, which is required to meet the characteristics of both on-region and off-region because a gate voltage applied to it ranges from about 15 to 20V. On the other hand, peripheral circuits to drive the pixel are composed mainly of CMOS circuits, which rely greatly on the characteristics of on-region.
Unfortunately, TFTs made of polysilicon film tend to increase in off-current (leakage current). This leads to a decrease in mobility and on-current after prolonged operation. A probable reason for this trouble is an increase in channel electric field which gives rise to hot carriers and deteriorates the characteristic properties.
A well-known way in the field of MOS transistor to prevent the deterioration of characteristic properties due to hot carriers, thereby improving reliability, is to adopt the LDD (Lightly Doped Drain) structure. This structure is characterized by an impurity region of lower concentration which is formed inside the source-drain region. This region is called LDD region. The LDD structure permits the off-current to be reduced more than the ordinary TFE structure.
MOS transistors are constructed such that the LDD region overlaps to some extent with the gate electrode, with a gate insulating film interposed between them. This structure is known as, for example, GOLD (Gate-drain overlapped LDD) and LATID (Large-tilt-angle implanted drain), which are made in different ways. These structures make it possible to reduce the impurity concentration in the LDD region, thereby reliving the electric field and improving the hot carrier resistance.
Attempts are being made to apply the technology of MOS transistor to TFT. For example, GOLD structure with side wall of silicon is reported in xe2x80x9cM. Hatano, H. Akimoto, and T. Sakai, IEDM97 TECHNICAL DIGEST, p. 523-526, 1997xe2x80x9d.
The structure reported in this paper presents difficulties in leaving the gate insulating film highly selectively in the anisotropic etching of film for the side wall. This leads to variation in characteristic properties.
In addition, the structure reported in this paper has a larger off-current (the current that flows when TFT is in off state) than the ordinary LDD structure. Therefore, when TFTs of the reported structure are used as switching elements to drive pixel electrodes, they consume more electric power and display anomalous images due to large off-current. The increase in off-current is due to the fact that an inversion layer is formed in the LDD region which overlaps with the gate electrode and this inversion layer functions as the hole passage.
The present invention was completed in order to overcome the above-mentioned problems. It is an object of the present invention to provide a first TFT of new structure in which the gate electrode overlaps with the LDD region. It is another object of the present invention to provide a second TFT of such structure in which the gate electrode does not overlap with the LDD region. It is further another object of the present invention to provide a technology to produce simultaneously a first TFT of new structure in which the gate electrode overlaps with the LDD region and a second TFT of such structure in which the gate electrode does not overlap with the LDD region. It is still further another object of the present invention to provide an excellent semiconductor device whose circuits are constructed of TFTs with high driving performance and TFTs with high reliability.
The first aspect of the present invention is a semiconductor device equipped with a first semiconductor element and a second semiconductor element on the same insulating surface, characterized in that said first semiconductor element has a gate insulating film, a first gate electrode formed adjacent to said gate insulating film, a second gate electrode which covers said first gate electrode and is formed adjacent to said gate insulating film, a channel-forming region which overlaps with the region in contact with said gate insulating film of said first gate electrode, with said gate insulating film interposed between them, and an impurity region which overlaps with the region in contact with said gate insulating film of said second gate electrode, with said gate insulating film interposed between them, and said second semiconductor element has said gate insulating film, a third gate electrode formed adjacent to said gate insulating film, and an impurity region which does not overlap with said third gate electrode.
The second aspect of the present invention is a semiconductor device equipped with a high voltage circuit consisting of a first semiconductor element and a high speed drive circuit consisting of a second semiconductor element on the same insulating surface, characterized in that said high voltage circuit consists of a first semiconductor element which has a gate insulating film, a first gate electrode formed adjacent to said gate insulating film, a second gate electrode which covers said first gate electrode and is formed adjacent to said gate insulating film, a channel-forming region which overlaps with the region in contact with said gate insulating film of said first gate electrode, with said gate insulating film interposed between them, and said high-speed drive circuit consists of a second semiconductor element which has said gate insulating film, a third gate electrode formed adjacent to said gate insulting film, and an impurity region which does not overlap with said third gate electrode.
The third aspect of the present invention is a semiconductor device containing pixels each formed from an n-channel type thin film transistor and CMOS circuits each formed from an n-channel type thin film transistor and a p-channel type thin film transistor, characterized in that the n-channel type thin film transistor of said pixels has a gate insulating film, a first gate electrode formed adjacent to said gate insulating film, a second gate electrode which covers said first gate electrode and is formed adjacent to said gate insulating film, a channel-forming region which overlaps with the region in contact with said gate insulating film of said first gate electrode, with said gate insulating film interposed between them, and an impurity region which overlaps with the region in contact with said gate insulating film of said second gate electrode, with said gate insulating interposed between them, and the n-channel type thin film transistor of said CMOS circuit has a gate insulating film, a third gate electrode formed adjacent to said gate insulating film, and an impurity region which does not overlap with said third gate electrode.
The foregoing structure is characterized in that said second semiconductor element does not have said second gate electrode.
The foregoing structure is characterized in that said impurity region is in contact with said channel forming region.
The foregoing structure is characterized in that said impurity region contains an impurity element of Group 15 in an amount of 1xc3x971016 to 1xc3x971019 atms/cm3.
The fourth aspect of the present invention is a semiconductor device containing CMOS circuits each formed from an n-channel type thin film transistor and a p-channel type thin film transistor, characterized in that said n-channel type thin film transistor has a gate insulating film, a first gate electrode formed adjacent to said gate insulating film, a second gate electrode which covers said first gate electrode and is formed adjacent to said gate insulating film, a channel-forming region which overlaps with the region in contact with said gate insulating film of said first gate electrode, with said gate insulating film interposed between them, and an impurity region which overlaps with the region in contact with said gate insulating film of said second gate electrode, with said gate insulating film interposed between them, and said p-channel type thin film transistor has a gate insulating film, a first gate electrode formed adjacent to said gate insulating film, and an impurity region which does not overlap with said first gate electrode.
The foregoing structure is characterized in that said first gate electrode is a single layer or multiple layer formed from a metal (as simple substance) or an alloy thereof, such as tantalum (Ta), tantalum nitride (TaN), titanium (Ti), chromium (Cr), tungsten (W), molybdenum (Mo), silicon (Si), aluminum (Al), and copper (Cu).
The foregoing structure is characterized in that the material for said second gate electrode is different from that for said first gate electrode.
The present invention is characterized by the structure of the first semiconductor element (the first thin film transistor) and the structure of the second semiconductor element (the second thin film transistor). Their production processes have their respective features.
The fifth aspect of the present invention is a process for producing a semiconductor device, said process comprising a first step of forming a first semiconductor layer and a second semiconductor layer on an insulating surface, a second step of forming a gate insulating film adjacent to said first semiconductor layer and said second semiconductor layer, a third step of forming a first gate electrode adjacent to said gate insulating film, a fourth step of forming a first impurity region by adding an element belonging to Group 15 to said first semiconductor layer and said second semiconductor layer by using said first gate electrode as a mask, a fifth step of forming a second gate electrode which covers said first gate electrode and is in contact with said gate insulating film, a sixth step of forming a second impurity region by adding an element belonging to Group 15 to said first semiconductor layer and said second semiconductor layer by using said second gate electrode as a mask, and a seventh step of removing only the second electrode formed on said second semiconductor layer, with said gate insulating film interposed between them.
The sixth aspect of the present invention is a process for producing a semiconductor device, said process comprising a first step of forming a first semiconductor layer and a second semiconductor layer on an insulating surface, a second step of forming a gate insulating film adjacent to said first semiconductor layer and said second semiconductor layer, a third step of forming a first gate electrode adjacent to said gate insulating film, a fourth step of forming a first impurity region by adding an element belonging to Group 15 to said first semiconductor layer and said second semiconductor layer by using said first gate electrode as a mask, a fifth step of forming a second gate electrode which covers said first gate electrode and is in contact with said gate insulating film, a sixth step of forming a second impurity region by adding an element belonging to Group 15 to said first semiconductor layer and said second semiconductor layer by using said second gate electrode as a mask, a seventh step of removing part of said second electrode, and an eighth step of removing only the second electrode formed on said second semiconductor layer, with said gate insulating film interposed between them.
The foregoing process is characterized in that said first impurity region has the LDD region formed therein and second impurity region has the source region and drain region formed therein.
The foregoing process is characterized in that said first impurity region contains an impurity element of Group 15 in an amount of 1xc3x971016 to 1xc3x971019 atms/cm3.
In the meantime, the term xe2x80x9cimpurityxe2x80x9d as used in this specification denotes elements belonging to Groups 13 or 15 of the periodic table, unless otherwise mentioned. The impurity regions may vary in its size (area) during the manufacturing process; however, they will be indicated by the same reference number in this specification unless they change in concentration even though they change in area.